1. Field of the Invention
The present disclosure relates to touch display technology, and more particularly to an in-cell touch display panel and an electronic device.
2. Discussion of the Related Art
With the development of touch display technology, In-cell touch display panels have been widely adopted by electronic devices, such as cellular phones. As the in-cell touch display panels integrate the touch and the display function, that is, the touch circuit and the display circuit are formed on the thin film transistor (TFT) array substrate, which is usually referred to as a TFT substrate. Such configuration contributes to a high transmission rate, and the electronic device may be designed to be lighter and thinner.
In-cell touch display panels may include self-capacitance and mutual-capacitance types. Regardless of the above-mentioned types, to integrate the touch and the display function, additional manufacturing processes are configured on the array circuit of the TFT substrate. The additional manufacturing processes include configuring a layer of metallic wiring to be the touch sensing wirings, which are usually configured on a topper layer of the TFT substrate. As the line width of the metallic wirings is thinner, and the film thickness is thicker, the metallic wirings can be easily seen on the TFT substrate. After the TFT substrate and the color filter (CF) are assembled, according to the conventional design of the liquid crystal panels, some of the photoresist spacers (PSs) between the TFT substrate and the CF are above the metallic wirings, and some of the PSs are not above the metallic wirings, which may cause the dark stripe issue on the liquid crystal panel. In addition, the issues such as insufficient surface pressure, un-recoverable Push Mura, and water ripples may occur.
Referring to FIGS. 1, 2, and 3, the in-cell touch display panels includes a TFT substrate 100, a CF substrate 200 opposite to the TFT substrate 100, a liquid crystal layer 300 between the TFT substrate 100 and the CF substrate 200, a plurality of PSs 400 between the TFT substrate 100 and the CF substrate 200. The TFT substrate 100 includes a flat layer 101, a common electrode layer 102, an inter-layer insulation layer 103 covering the common electrode layer 102, a metallic layer 104 above the inter-layer insulation layer 103, a protection layer 105 covering the metallic layer 104, and a pixel electrode layer 106 covering the protection layer 105. Usually, a substrate layer, a gate layer, an active layer, a source/drain layer, and a plurality of insulation layers are arranged below the flat layer.
The common electrode layer 102 includes a plurality of touch electrodes 1021 spaced apart from each other, and the touch electrodes 1021 are arranged in a matrix. The metallic layer 104 includes a plurality of touch sensing lines 1041 and a plurality of dummy lines 1042 corresponding to each of the touch electrodes 1021. The touch sensing lines 1041 pass through the through holes (not shown) on the inter-layer insulation layer 103 to contact the touch electrodes 1021 so as to connect each of the touch electrodes 1021 to a touch driving chip 900. The dummy lines 1042 are disconnected on a gap between two adjacent touch electrodes 1021.
As the film thickness of the metallic layer 104 is large, the pattern directly affect the outline of the TFT substrate 100. With respect to the PS 400 design of conventional in-cell touch display panels, the PSs 400 are arranged in accordance with rules, that is, the pattern of the metallic layer 104 has not been considered. Most of the PSs 400 are arranged above the dummy lines 1042, and a portion of the PSs 400 may be above the gap of the two adjacent touch electrodes 1021, that is, the disconnected portion of the dummy lines 1042. When the TFT substrate 100 and the CF substrate 200 are assembled, some of the PSs 400 may touch the dummy lines 1042 or the disconnected portion of the dummy lines 1042. Also, as the line width of the dummy lines 1042 is about 3 um, and the width of the PS 400 is about 6 um, this may result in unstable PSs 400. As such, the surface pressure of the panel may not be enough, which not only may affect the strength of the product, but also may cause un-recoverable Push Mura, water ripple, and bright and dark spots. In addition, as some of the PSs 400 are not above the dummy lines 1042, the cell thickness may be smaller, compared to the location where the PSs 400 are above the dummy lines 1042. Thus, the transmission rate of the panel may be greater, and so does the brightness, which may cause dark stripe on the gap of two adjacent touch electrodes 1021.